1. Field of the Invention
The present invention relates to nonvolatile memory devices; and more specifically, the invention relates to a nonvolatile memory device that, using variable resistor elements permitting an electric resistance to be variable for each memory cell, is capable of storing. 2-level, 3-level, or a larger multi-level data into one memory cell by utilizing variations in the electric resistance.
2. Description of the Related Art
Nonvolatile memory devices are widely used by being mounted in various mobile apparatuses, such as cellular phones, IC cards, and digital cameras. In recent years, in line with increasing opportunities of handling image data, demands have been growing for nonvolatile memories capable of storing even larger amount of data and operating at higher speed. In addition, since such nonvolatile memory devices are intended for use with mobile apparatuses, demands for low power consumption are even more strongly growing.
Under these circumstances, nonvolatile memory devices currently on a mainstream are represented by flash memories that store data by controlling electrical charges accumulating in floating gates. However, since the nonvolatile memory devices have a structure in which electrical charges are accumulated in the floating gates with high electric fields, the cell structure is complex to an extent of giving rise to problems in implementing high integration.
As nonvolatile memory devices for solving these problems, electrically erasable phase transition memories (ovonic unified memories (OUMs)) have been proposed. One device of this type is disclosed in, for example, Japanese Unexamined Patent Publication No. 05-21740. In detail, Japanese Unexamined Patent Publication No. 05-21740 discloses an electrically erasable phase transition memory in which two states, namely crystalline and noncrystalline states, of a memory layer are used to perform programming and erasure. Compared to a flash memory, the disclosed memory has a simpler memory structure, so that, theoretically, it can be integrated higher than the flash memory.
As another technique for solving the problem of insufficient storage capacity, there are multi-level nonvolatile memory techniques for storing 3-level or larger multi-level data in one cell. For example, Japanese Unexamined Patent Publication No. 2002-203392 discloses a multi-level nonvolatile memory that uses an OUM memory to store the multi-level data.
However, OUM memories according to conventional techniques use principles of storing the data in the manner that the memory layer is electrically controlled to change between the two states, i.e., crystalline and noncrystalline states, and therefore give problems of making it difficult to accurately control the states at 3-level or larger multi-level to be stored in variable resistor elements formed of a single property material. A memory element of the multi-level nonvolatile memory device disclosed in Japanese Unexamined Patent Publication No. 2002-203392 is implemented by having multiple layers formed using OUM materials having different properties (crystallizing temperature, crystallizing time, and melting point temperature). However, the memory element gives to a problem of increasing manufacturing steps. In addition, there arises another problem in that, when the number of program levels is increased, correspondingly increased types of OUM materials have to be used. In addition, since programming/erasure is performed on the variable resistor element by electrically conducting temperature control using heat generation means provided in proximity to the memory layer, considerations should be taken into account in avoiding thermal disturbance between adjacent cells. In addition, since heat needs to be generated using electrical means, the program current is considerably large as about 1 mA per memory cell, so that correspondingly thick wires should be used, thereby leading to the problem of making it difficult to implementing a simple reduction in the memory cell area. As such, a simple reduction of the memory cell cannot be implemented in proportion to reduced manufacturing process rules. In other words, there arises a problem that scaling rules made in considerations only on electrical properties cannot be applied. According to present-stage simulations regarding OUM materials, a memory-cell size limit is reported to be 0.065 μm (refer to, for example, “42nd Nikkei Microdevice Seminars—Nonvolatile Memory Technology Forefront,” pp. 1 to 26).
As described above, the nonvolatile memory devices according to the conventional techniques are not capable of sufficiently satisfying user demands for large storage capacity, high-speed operation, and low power consumption.